參數(shù)資料
型號: 935211970551
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: PLASTIC, SOT-393, QFP-64
文件頁數(shù): 32/67頁
文件大?。?/td> 443K
代理商: 935211970551
1998 May 15
38
Philips Semiconductors
Product specication
Video Input Processor (VIP)
SAA7111
16.2.1
SUBADDRESS 00
Table 10 Chip version SA 00, D7 to D0
Note
1. The I2C-bus subaddress 00 has to be initialized with 0 prior to reading it.
16.2.2
SUBADDRESS 02
Table 11 Analog control 1 (mode select; see Figs 28 to 35) SA 02, D2 to D0; note 1
Note
1. For modes 0 to 3 use BYPS (SA 09, D7) = 0 (chrominance trap active) and for modes 4 to 7 use BYPS = 1
(chrominance trap bypassed).
Table 12 Analog control 1 SA 02, D5 to D3 (see Fig.11)
Table 13 Analog control 1 SA 02, D7 and D6
FUNCTION
CONTROL BITS
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
Chip version in read mode(1)
00
0
X
chip version number
reserved for chip name
FUNCTION
CONTROL BITS D2 TO D0
MODE 2
MODE 1
MODE 0
Mode 0: CVBS (automatic gain)
0
Mode 1: CVBS (automatic gain)
0
1
Mode 2: CVBS (automatic gain)
0
1
0
Mode 3: CVBS (automatic gain)
0
1
Mode 4: Y (automatic gain) + C (gain channel 2 xed to GAI2 level)
1
0
Mode 5: Y (automatic gain) + C (gain channel 2 xed to GAI2 level)
1
0
1
Mode 6: Y (automatic gain) + C (gain channel 2 adapted to Y gain)
1
0
Mode 7: Y (automatic gain) + C (gain channel 2 adapted to Y gain)
1
DECIMAL VALUE
UPDATE HYSTERESIS FOR 9-BIT GAIN
CONTROL BITS D5 TO D3
GUDL 2
GUDL 1
GUDL 0
0....
off
0
....7
±7 LSB
1
ANALOG FUNCTION SELECT FUSE
CONTROL BITS D7 AND D6
FUSE 1
FUSE 0
Amplier plus anti-alias lter bypassed
0
01
Amplier active
1
0
Amplier plus anti-alias lter active
1
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