參數(shù)資料
型號： 935209270118
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： LVT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14
文件頁數(shù)： 8/13頁
文件大小： 175K
代理商： 935209270118
Philips Semiconductors
Product specification
74LVT74
3.3V Dual D-type flip-flop
1996 Aug 28
4
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions
Voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
°C to +85°C
UNIT
MIN
TYP1
MAX
VIK
Input clamp voltage
VCC = 2.7V; IIK = –18mA
–1.2
V
VCC = 2.7 to 3.6V; IOH = –100A
VCC–0.2
VOH
High-level output voltage
VCC = 2.7V; IOH = –6mA
2.4
V
VCC = 3.0V; IOH = –20mA
2.0
VCC = 2.7V; IOL = 100A
0.2
VOL
Low-level output voltage
VCC = 2.7V; IOL = 24mA
0.5
V
VCC = 3.0V; IOL = 32mA
0.5
II
Input leakage current
VCC = 0 or 3.6V; VI = 5.5V
10
A
II
In ut leakage current
VCC = 3.6V; VI = VCC or GND
±1
A
IOFF
Output off current
VCC = 0V; VI or VO = 0 to 4.5V
±100
A
ICC
Quiescent supply current
VCC = 3.6V; Outputs High, VI = GND or
VCC, IO = 0
0.5
1
mA
ICC
Additional supply current per input pin2
VCC = 3V to 3.6V; One input at VCC–0.6V,
Other inputs at VCC or GND
0.2
A
CI
Input capacitance
VI = 3V or 0
3
pF
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specificed voltage level other than VCC or GND.
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500; Tamb = –40°C to +85°C.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3V ± 0.3V
VCC = 2.7V
UNIT
MIN
TYP1
MAX
fMAX
Maximum clock frequency
1
150
345
MHz
tPLH
tPHL
Propagation delay
CPn to Qn or Qn
1
1.0
3.1
3.6
4.8
5.0
5.8
5.0
ns
tPLH
tPHL
Propagation delay
SDn, RDn to Qn or Qn
2
1.0
3.1
3.0
5.0
4.4
6.2
4.8
ns
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3V ± 0.3V
VCC = 2.7V
UNIT
MIN
TYP
MIN
tS (H)
tS (L)
Setup time
Dn to CPn
1
1.7
1.4
0.6
0.4
1.8
1.6
ns
th (H)
th (L)
Holdtime
Dn to CPn
1
0.3
0
–0.3
–0.6
0.3
0
ns
tW (H)
tW (L)
CPn Pulse Width
1
2.0
1.0
1.2
3.0
ns
tW (L)
SDn, RDn Pulse Width
2
2.0
1.0
3.0
trec
Recovery time
SDn, RDn tp CPn
3
0.5
–0.3
0.5
ns
相關(guān)PDF資料
PDF描述
935209250118 LVT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
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