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參數(shù)資料
| 型號： | 935207290118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, 20 1-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP2-56 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 119K |
| 代理商： | 935207290118 |
Philips Semiconductors
Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25 °C
Tamb = –40 °C
to +85
°C
UNIT
Min
Typ
Max
Min
Max
VIK
Input clamp voltage
VCC = 4.5 V; IIK = –18 mA
–0.9
–1.2
V
VCC = 4.5 V; IOH = –3 mA; VI = VIL or VIH
2.5
2.9
2.5
V
VOH
HIGH-level output voltage
VCC = 5.0 V; IOH = –3 mA; VI = VIL or VIH
3.0
3.4
3.0
V
VCC = 4.5 V; IOH = –32 mA; VI = VIL or VIH
2.0
2.4
2.0
V
VOL
LOW-level output voltage
VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH
0.36
0.55
V
VRST
Power-up output voltage3
VCC = 5.5 V; IO = 1 mA; VI = GND or VCC
0.13
0.55
V
II
Input leakage current
VCC = 5.5 V; VI = VCC or GND
±0.01
±1.0
A
VCC = 5.5 V; VI = VCC or GND
Control pins
±0.01
±1
A
II
Input leakage current
74ABTH16821A
VCC = 5.5 V; VI = VCC
Data pins
0.01
1
A
74ABTH16821A
VCC = 5.5 V; VI = 0
Data pins
–1
–3
–5
A
5
VCC = 4.5 V; VI = 0.8 V
35
IHOLD
Bus Hold current inputs5
74ABTH16821A
VCC = 4.5 V; VI = 2.0 V
–75
A
74ABTH16821A
VCC = 5.5 V; VI = 0 to 5.5 V
±800
IOFF
Power-off leakage current
VCC = 0.0 V; VO or VI ≤ 4.5 V
±5.0
±100
A
IPU/PD
Power-up/down 3-State
output current4
VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC;
VOE = Don’t care
±5.0
±50
A
IOZH
3-State output HIGH current
VCC = 5.5 V; VO = 2.7 V; VI = VIL or VIH
1.0
10
A
IOZL
3-State output LOW current
VCC = 5.5 V; VO = 0.5 V; VI = VIL or VIH
–1.0
–10
A
ICEX
Output HIGH leakage
current
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC
5.0
50
A
IO
Output current1
VCC = 5.5 V; VO = 2.5 V
–50
–90
–180
–50
–180
mA
ICCH
VCC = 5.5 V; Outputs HIGH, VI = GND or VCC
0.5
1
mA
ICCL
Quiescent supply current
VCC = 5.5 V; Outputs LOW, VI = GND or VCC
10
19
mA
ICCZ
VCC = 5.5 V; Outputs 3-State; VI = GND or VCC
0.5
1
mA
ICC
Additional supply current
per input pin2
VCC = 5.5 V; one input at 3.4 V, other inputs at
VCC or GND
0.25
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 msec. From VCC = 2.1 V to VCC = 5 V a
transition time of up to 100
sec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
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