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參數(shù)資料
| 型號： | 935206210518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, SOT-188, LCC-68 |
| 文件頁數(shù)： | 56/67頁 |
| 文件大?。?/td> | 443K |
| 代理商： | 935206210518 |
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1998 May 15
6
Philips Semiconductors
Product specication
Video Input Processor (VIP)
SAA7111
7
PINNING
SYMBOL
PINS
I/O
DESCRIPTION
PLCC68
QFP64
TRST
1
58
I
Test reset input not (active LOW), for boundary scan test;
notes 1, 2, 3 and 4.
TCK
2
59
I
Test clock input for boundary scan test; note 3.
RTCO
3
60
O
Real time control output: contains information about actual system
clock frequency, subcarrier frequency and phase and PAL sequence.
IICSA
4
61
I
I2C-bus slave address select input; 0
→ 48H for write, 49H for read,
1
→ 4AH for write, 4BH for read.
SDA
5
62
I/O
I2C-bus serial data input/output.
SCL
6
63
I/O
I2C-bus serial clock input/output.
n.c.
7
64
Not connected.
n.c.
8
Not connected.
n.c.
9
Not connected.
n.c.
10
1
Not connected.
TDO
11
2
O
Test data output for boundary scan test; note 3.
TDI
12
3
I
Test data input for boundary scan test; note 3.
TMS
13
4
I
Test mode select input for boundary scan test or scan test; note 3.
VSSA2
14
5
GND
Ground for analog supply voltage channel 2.
AI22
15
6
I
Analog input 22.
VDDA2
16
7
P
Positive supply voltage (+5 V) for analog channel 2.
AI21
17
8
I
Analog input 21.
VSSA1
18
9
GND
Ground for analog supply voltage channel 1.
AI12
19
10
I
Analog input 12.
VDDA1
20
11
P
Positive supply voltage (+5 V) for analog channel 1.
AI11
21
12
I
Analog input 11.
VSSS
22
13
GND
Substrate (connected to analog ground).
AOUT
23
14
O
Analog test output; for testing the analog input channels.
VDDA0
24
15
P
Positive supply voltage (+5 V) for internal CGC.
VSSA0
25
16
GND
Ground for internal CGC.
VREF
26
17
O
Vertical reference output signal (I2C-bit COMPO = 0) or inverse
composite blank signal (I2C-bit COMPO = 1) (enabled via I2C-bit
OEHV).
VDD5
27
18
P
Positive digital supply voltage 5 (+5 V).
VSS5
28
19
GND
Digital ground for positive supply voltage 5.
LLC
29
20
O
Line-locked system clock output (27 MHz).
LLC2
30
21
O
Line-locked clock 1
2 output (13.5 MHz).
CREF
31
22
O
Clock reference output: this is a clock qualier signal distributed by
the CGC for a data rate of LLC2. Using CREF all interfaces on the
VPO-bus are able to generate a bus timing with identical phase.
If CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an
inverse composite blank signal (pixel qualier) is provided on this pin.
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