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參數(shù)資料
| 型號： | 935196770112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, 20 1-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP3-56 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 121K |
| 代理商： | 935196770112 |
Philips Semiconductors
Product data
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
2
2002 Dec 17
FEATURES
High speed parallel latches
Live insertion/extraction permitted
Extra data width for wide address/data paths or buses carrying
parity
Power-up 3-State
74ABTH16841A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Power-up reset
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Output capability: +64 mA / –32 mA
Latch-up protection exceeds 500 mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is HIGH. This allows asynchronous operation,
as the output transition follows the data in transition. On the nLE
HIGH-to-LOW transition, the data that meets the set-up and hold
time is latched.
Data appears on the bus when the Output Enable (nOE) is LOW.
When nOE is HIGH the output is in the high-impedance state.
Two options are available, 74ABT16841A which does not have the
bus-hold feature and 74ABTH16841A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25 °C; GND = 0 V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
nDx to nQx
CL = 50 pF; VCC = 5 V
3.1
2.2
ns
CIN
Input capacitance
VI = 0 V or VCC
4
pF
COUT
Output capacitance
VO = 0 V or VCC; 3-State
7
pF
ICCZ
Quiescent supply current
Outputs disabled; VCC = 5.5 V
500
A
ICCL
Quiescent supply current
Outputs LOW; VCC = 5.5 V
10
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
PART NUMBER
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°C to +85 °C
74ABT16841ADL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85 °C
74ABT16841ADGG
SOT364-1
56-Pin Plastic SSOP Type III
–40
°C to +85 °C
74ABTH16841ADL
SOT371-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
1D0 – 1D9
2D0 – 2D9
Data inputs
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1Q0 – 1Q9
2Q0 – 2Q9
Data outputs
1, 28
1OE, 2OE
Output enable inputs (active-LOW)
56, 29
1LE, 2LE
Latch enable inputs (active rising edge)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0 V)
7, 22, 35, 50
VCC
Positive supply voltage
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