參數(shù)資料
型號： 935190320112
廠商： NXP SEMICONDUCTORS
元件分類： 計(jì)數(shù)器
英文描述： HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDSO14
封裝： PLASTIC, SSOP-14
文件頁數(shù)： 6/7頁
文件大小： 43K
代理商： 935190320112
December 1990
6
Philips Semiconductors
Product specication
4-bit binary ripple counter
74HC/HCT93
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (
ICC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
CP0, CP1
MRn
0.60
0.40
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP0 to Q0
18
34
43
51
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
CP1 to Q1
18
34
43
51
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
CP1 to Q2
24
46
58
69
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
CP1 to Q3
30
58
73
87
ns
4.5
Fig.6
tPHL
propagation delay
MRn to Qn
17
33
41
50
ns
4.5
Fig.7
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.6
trem
removal time
MRn to CP0, CP1
10
3
13
15
ns
4.5
Fig.7
tW
pulse width
CP0, CP1
16
7
20
24
ns
4.5
Fig.6
tW
master reset pulse width
MRn
16
5
20
24
ns
4.5
Fig.7
fmax
maximum clock pulse
frequency
CP0, CP1
30
70
24
20
MHz
4.5
Fig.6
相關(guān)PDF資料
PDF描述
933825560005 HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, UUC
0560-6600-63 ADSL Magnetics For Analog Devices AD20MSP910
933756960112 HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDIP14
0560-6600-62 TELECOM TRANSFORMER
933825550005 HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, UUC
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