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參數(shù)資料
| 型號(hào)： | 935189660118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 封裝： | SOT-338-1, SSOP-16 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 145K |
| 代理商： | 935189660118 |
Philips Semiconductors - PIP - 74HC/HCT137; 3-to-8 line decoder/demultiplexer with address latches; inverting
Product Information
74HC/HCT137; 3-to-8
line
decoder/demultiplexer
with address latches;
inverting
Information as of 2003-04-22
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Download datasheet
Applications
Block diagram
topGeneral description
The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT137 are 3-to-8 line decoder/demultiplexers with latches at the three address inputs (An). The '137'
essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW),
the '137' acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data
present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE
remains HIGH.
The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch
operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The '137' is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address)
applications in bus oriented systems.
topFeatures
q
Combines 3-to-8 decoder with 3-bit latch
q
Multiple input enable for easy expansion or independent controls
q
Active LOW mutually exclusive outputs
q
Output capability: standard
q
ICC category: MSI
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74HC137N.html (1 of 4) [Apr-30-2003 10:21:40 AM]
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