參數(shù)資料
型號(hào)： 935188310112
廠商： NXP SEMICONDUCTORS
元件分類： 計(jì)數(shù)器
英文描述： HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
封裝： SOT-403-1, TSSOP-16
文件頁(yè)數(shù)： 10/12頁(yè)
文件大?。?/td> 80K
代理商： 935188310112
December 1990
7
Philips Semiconductors
Product specication
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
61
22
18
190
38
32
240
48
41
285
57
48
ns
2.0
4.5
6.0
Fig.8
tPHL/ tPLH
propagation delay
CP to TC
69
25
20
215
43
37
270
54
46
325
65
55
ns
2.0
4.5
6.0
Fig.8
tPHL
propagation delay
MR to Qn
63
23
18
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig.9
tPHL
propagation delay
MR to TC
63
23
18
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig.9
tPHL/ tPLH
propagation delay
CET to TC
33
12
10
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.10
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 8 and 10
tW
clock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
tW
master reset pulse
width; LOW
80
16
14
19
7
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.9
trem
removal time
MR to CP
100
20
17
19
7
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.9
tsu
set-up time
Dn to CP
80
16
14
25
9
7
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.11
tsu
set-up time
PE to CP
100
20
17
30
11
9
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.11
相關(guān)PDF資料
PDF描述
935188570112 HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
933669370652 HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
933714520652 HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
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