參數(shù)資料
型號(hào)： 935187130557
廠商： NXP SEMICONDUCTORS
元件分類： 畫面疊加
英文描述： PICTURE-IN-PICTURE IC, PQFP100
封裝： PLASTIC, SOT-317-2, QFP-100
文件頁(yè)數(shù)： 22/43頁(yè)
文件大小： 250K
代理商： 935187130557
February 1995
29
Philips Semiconductors
Preliminary specication
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
External memory
For the external memory two VDRAMS of type Mitsubishi
M5442256 are used. They have a storage capacity of
262144 words of 4-bit each and will be used in parallel.
An overview of the timing to the VDRAM is depicted in
Fig.19. Three different timing modes are shown. If the
SAB9075 is not in one of these three modes, it is in idle
mode in which all the control signals are HIGH. An idle
mode takes at least 4 clock periods. Switching from one
mode to another is always carried out via this idle mode.
The clock signal shown is an internal clock derived from
the PLLs and is approximately 27 MHz.
Main and sub-ADCs
Both main and sub-channels convert the analog input
signals to digital signals by three ADCs for each channel.
The input levels of the ADCs are equal and can set by the
MAVrefT, SAVrefT, MAVrefB, and SAVrefB pins.The
reference levels are made internally by a resistor network
which divides the analog VDD to a default set of preferred
signal levels of 1.5 V. If the application requires a different
set of levels the internal resistors can be shunted. External
capacitors are required to filter AC components on the
reference levels.
The resolution of the ADCs is 6-bit and the sampling is
carried out at the system frequency of 27 MHz. The
bias current Ibias is made internally but can be increased or
decreased.
The inputs should be AC-coupled and an internal clamping
circuit will clamp the input to MAVrefB and SAVrefB for the
luminance channels and to
for the chrominance channels. The clamping starts at the
active edge of the burstkey.
For more information see chapter “Test and application
information”.
MAV
refT
MAV
refB
+
2
-----------------------------------------------------
LSB
2
------------
+
SAV
refT
SAV
refB
+
2
---------------------------------------------------
LSB
2
------------
+
Output DACs
The digital processed signals are converted to analog
signals by means of three DACs. The output voltages of
these DACs are default set by the DAVrefTU, DAVrefTV and
DAVrefTY pins for the TOP-levels. Default signal levels are
1.5 V. The output buffer after each DAC is a PMOS source
follower.
For more information see chapter “Test and application
information”.
HUE and SAT DACs
The HUE and SAT DACs are resistor DACs based on a
R2R network. They have a direct control from their I2C-bus
register and therefore their sample frequency is limited by
the I2C-bus frequency. The output voltage is linear with the
I2CVDD. Therefore the VDD of this block is a separate pin.
PLLs and clock generation
The SAB9075H has two PLLs on-board, one for the sub-
channel and one for the main-channel and the display part.
The PLLs lock to the input signals MHsync and SHsync. The
internal clock frequency is 1 728 times higher which is
approximately 27 MHz in a standard NTSC system.
The positive edges of the Hsync signals are the driving
timing points. For good short term stability they have to be
noise/jitter free.
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