參數(shù)資料
型號： 935185830112
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁數(shù)： 6/8頁
文件大?。?/td> 56K
代理商： 935185830112
September 1993
6
Philips Semiconductors
Product specication
Octal D-type ip-op with reset;
positive-edge trigger
74HC/HCT273
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (
ICC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
MR
CP
Dn
1.00
1.75
0.15
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
16
30
38
45
ns
4.5
Fig.6
tPHL
propagation delay
MR to Qn
23
34
43
51
ns
4.5
Fig.7
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.6
tW
clock pulse width
HIGH or LOW
16
9
20
24
ns
4.5
Fig.6
tW
master reset pulse width
LOW
16
8
20
24
ns
4.5
Fig.7
trem
removal time
MR to CP
10
2
13
15
ns
4.5
Fig.7
tsu
set-up time
Dn to CP
12
5
15
18
ns
4.5
Fig.8
th
hold time
Dn to CP
3
4
3
ns
4.5
Fig.8
fmax
maximum clock pulse
frequency
30
56
24
20
MHz
4.5
Fig.6
相關(guān)PDF資料
PDF描述
935183580112 HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
933715440652 HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
935174730112 HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
933715440653 HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
933670560652 HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20
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