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參數(shù)資料
| 型號(hào)： | 935178900112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 4.40 MM, PLASTIC, SOT-355-1, TSSOP-24 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 151K |
| 代理商： | 935178900112 |
Philips Semiconductors - PIP - 74ABT657; Octal transceiver with parity generator/checker (3-State)
Product Information
74ABT657; Octal
transceiver with
parity
generator/checker
(3-State)
Information as of 2003-04-22
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Download datasheet
topGeneral description
The 74ABT657 high-performance BiCMOS device combines low static and dynamic power dissipation with high
speed and high output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-State outputs and an 8-bit parity
generator/checker, and is intended for bus-oriented applications. The buffers have a guaranteed current sinking
capability of 64mA. The Transmit/Receive (T/R) input determines the direction of the data flow through the
bidirectional transceivers. Transmit (active-High) enables data from A ports to B ports; Receive (active-Low) enables
data from B ports to A ports.
The Output Enable (OE) input disables both the A and B ports by placing them in a high impedance condition when
the OE input is High. The parity select (ODD/EVEN) input gives the user the option of odd or even parity systems.
The parity (PARITY) pin is an output from the generator/checker when transmitting from the port A to B (T/R =
High) and an input when receiving from port B to A port (T/R = Low). When transmitting (T/R = High) the parity
select (ODD/EVEN) input is set, then the A port data is polled to determine the number of High bits. The parity
(PARITY) output then goes to the logic state determined by the parity select (ODD/EVEN) setting and by the number
of High bits on port A. For example, if the parity select (ODD/EVEN) is set Low (even parity), and the number of
High bits on port A is odd, then the parity (PARITY) output will be High, transmitting even parity. If the number of
High bits on port A is even, then the parity (PARITY) output will be Low, keeping even parity. When in receive
mode (T/R = Low) the B port is polled to determine the number of High bits. If parity select (ODD/EVEN) is Low
(even parity) and the number of Highs on port B is:
1. odd and the parity (PARITY) input is High, then ERROR will be High, signifying no error.
2. even and the parity (PARITY) input is High, then ERROR will be asserted Low, indicating an error.
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74ABT657D.html (1 of 4) [May-08-2003 4:12:30 PM]
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