參數(shù)資料
型號： 935175150112
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14
文件頁數(shù)： 16/18頁
文件大小： 178K
代理商： 935175150112
1998 Feb 23
7
Philips Semiconductors
Product specication
Dual D-type ip-op with set and reset;
positive-edge trigger
74HC/HCT74
AC WAVEFORMS
Fig.6
Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD
to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse
frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
handbook, full pagewidth
trem
tW
tPLH
trem
VM
(1)
VM
(1)
VM
(1)
VM
(1)
nQ OUTPUT
tPHL
tPLH
tPHL
VM
(1)
nRD INPUT
nSD INPUT
nCP INPUT
nQ OUTPUT
MGL350
Fig.7
Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set
and reset pulse widths and the nRD, nSD to nCP removal time.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
相關(guān)PDF資料
PDF描述
935175180112 HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
933713390653 HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935175170112 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935175170118 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935175180118 HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
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