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參數(shù)資料
| 型號： | 935166080112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AC, SOT-338-1, SSOP2-16 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 935166080112 |
Philips Semiconductors
Product specification
74LV4060
14-stage binary ripple counter with oscillator
2
1998 Jun 23
853-2076 19619
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for Low Voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C.
Typical V
OHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb
= 25
°C.
All active components on chip
RC or crystal oscillator configuration
Output capability: standard (except for R
TC and CTC)
I
CC category: MSI
APPLICATIONS
Control Counters
Timers
Frequency Dividers
Time-delay circuits
DESCRIPTION
The 74LV4060 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT4060.
The 74LV4060 is a 14-stage ripple-carry counter/divider and
oscillator with three oscillator terminals (RS, RTC and CTC), ten
buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding
asynchronous master reset (MR). The oscillator configuration allows
design of either RC or crystal oscillator circuits. The oscillator may
be replaced by an external clock signal at input RS. In this case,
keep the oscillator pins (RTC and CTC) floating.
The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q3 to Q9 and Q11 to
Q13 = LOW), independent of the other input conditions.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf < 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
CL = 15 pF
RS to Q3
VCC = 3.3 V
29
tPHL/tPLH
Qn to Qn+1
6
ns
tPHL
MR to Qn
16
f
Maximum clock frequency
99
MHz
fmax
Maximum clock frequency
99
MHz
C1
Input capacitance
3.5
pF
C
Power dissipation capacitance per package
Notes 1, 2 and 3
40
pF
CPD
Power dissipation capacitance per package
40
pF
NOTES:
1. CPD is used to determine the dynamic power
dissipation (PD in mW)
PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL x VCC2 x fo) = sum of the outputs.
2. The condition is V1 = GND to VCC
3. For formula on dynamic power dissipation, see the
following pages.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°C to +125°C
74LV4060 N
SOT38-4
16-Pin Plastic SO
–40
°C to +125°C
74LV4060 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV4060 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV4060 PW
74LV4060PW DH
SOT403-1
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