
1996 Jan 26
22
Philips Semiconductors
Objective specication
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
FLYBACK PULSE INPUT (PIN 41)
VHSW
switching voltage level for horizontal
blanking
0.4
V
V2(SW)
switching level for phase-2 loop
4.0
V
V41(max)
maximum input voltage
note 7
8.0
V
Zi
input impedance
note 7
10
M
SANDCASTLE PULSE OUTPUT (PIN 39)
V39
output voltage
during burst key
4.8
5.3
5.8
V
during blanking
1.8
2.0
2.2
V
tW
pulse width
burst key pulse
3.3
3.5
3.7
s
vertical blanking (50 Hz)
25
lines
vertical blanking (60 Hz)
21
lines
Vclamp
clamping voltage level for vertical
guard detection
2.7
V
I39(min)
minimum input current to activate
guard detection
0.5
mA
I39(max)
maximum allowable input current
2.5
mA
td
delay of start of burst key to start of
sync
5.4
s
Vertical synchronization and geometry correction
VERTICAL OSCILLATOR; note 15
ffr
free running frequency
50/60
Hz
flock
locking frequency range
45
64.5
Hz
divider value not locked
625/525
lines
LR
locking range
488
722
lines/
frame
VERTICAL RAMP GENERATOR (PIN 50)
V50(p-p)
sawtooth voltage amplitude
(peak-to-peak value)
VS = 1FH;
C = 100 nF; R = 39 k
3.5
V
Idis
discharge current
1
mA
Icharge
charge current set by external
resistor
note 16
19
A
VS
vertical slope control range
63 steps
20
+20
%
I
50
charge current increase
f = 60 Hz
20
%
V50L
LOW level voltage of ramp
2.07
V
VERTICAL DRIVE OUTPUTS (PINS 47 AND 48)
Idiff(p-p)
differential output current
(peak-to-peak value)
VA = 1FH
0.95
mA
ICM
common mode output current
400
A
Vo
output voltage
0
4.0
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT