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參數(shù)資料
| 型號： | 935084690118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | F/FAST SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 111K |
| 代理商： | 935084690118 |
Philips Semiconductors
Product data
74F657
Octal transceiver with 8-bit parity generator/checker
2
2003 Feb 04
853 1117 00081
FEATURES
Combines 74F245 and 74F280A functions in one package
High impedance base input for reduced loading (70 A in HIGH
and LOW states)
Ideal in applications where high output drive and light bus loading
are required (IIL is 70 A versus FAST std of 600 A)
3-state buffer outputs sink 64 mA and source 15 mA
Input diodes for termination effects
24-pin plastic slim DIP (300 mil) package
Industrial temperature range available (–40 °C to +85 °C)
DESCRIPTION
The 74F657 is an octal transceiver featuring non-inverting buffers
with 3-state outputs and an 8-bit parity generator/checker, and is
intended for bus-oriented applications. The buffers have a
guaranteed current sinking capability of 24 mA at the A ports and
64 mA at the B ports. The transmit/receive (T/R) input determines
the direction of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from A ports to B ports; receive
(active LOW) enables data from B ports to A ports.
The output enable (OE) input disables both the A and B ports by
placing them in a high impedance condition when the OE input is
HIGH.
The parity select (ODD/EVEN) input gives the user the option of
odd or even parity systems.
The parity (PARITY) pin is an output from the generator/checker
when transmitting from the port A to B (T/R = HIGH) and an input
when receiving from port B to A port ( T/R = LOW).
When transmitting (T/R = HIGH) the parity select (ODD/EVEN) input
is set, then the A port data is polled to determined the number of
high bits. The parity (PARITY) output then goes to the logic state
determined by the parity select (ODD/EVEN) setting and by the
number of high bits on port A.
For example, if the parity select (ODD/EVEN) is set LOW (even
parity), and the number of high bits on port A is odd, then the parity
(PARITY) output will be HIGH, transmitting even parity. If the
number of high bits on port A is even, then the parity (PARITY)
output will be LOW, keeping even parity.
When in receive mode (T/R = LOW) the B port is polled to determine
the number of high bits. If parity select (ODD/EVEN) is LOW (even
parity) and the number of highs on port B is:
(1) odd and the parity (PARITY) input is HIGH, then ERROR will be
HIGH, significantly no error.
(2) even and the parity (PARITY) input is HIGH, then ERROR will be
asserted LOW, indicating an error.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT (TOTAL)
74F657
8.0ns
100 mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
INDUSTRIAL RANGE
DESCRIPTION
VCC = 5 V ±10%,
VCC = 5V ±10%,
PKG DWG #
Tamb = 0 °C to +70 °C
Tamb = –40 °C to +85 °C
24-pin plastic slim DIP (300 mil)
N74F657N
I74F657N
SOT222-1
24-pin plastic SOL
N74F657D
I74F657D
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH / LOW
LOAD VALUE
HIGH / LOW
A0–A7
A ports 3–state inputs
3.5 / 0.117
70
A / 70 A
B0–B7
B ports 3–state inputs
3.5 / 0.117
70
A / 70 A
PARITY
Parity input
3.5 / 0.117
70
A / 70 A
T/R
Transmit/receive input
2.0 / 0.066
40
A / 40 A
ODD/EVEN
Parity select input
1.0 / 0.033
20
A / 20 A
OE
Output enable input (active LOW)
2.0 / 0.066
40
A / 40 A
A0–A7
A ports 3–state outputs
150 / 40
3.0 mA / 24 mA
B0–B7
B ports 3–state outputs
750 / 106.7
15 mA / 64 mA
PARITY
Parity output
750 / 106.7
15 mA / 64 mA
ERROR
Error output
750 / 106.7
15 mA / 64 mA
NOTE:
1. One (1.0) FAST unit load is defined as: 20
A in the HIGH state and 0.6 mA in the LOW state.
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