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參數(shù)資料
| 型號(hào)： | 935053480512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), EQUALIZER CIRCUIT, PDSO32 |
| 封裝： | PLASTIC, SO-32 |
| 文件頁(yè)數(shù)： | 19/19頁(yè) |
| 文件大小： | 212K |
| 代理商： | 935053480512 |
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May 1991
9
Philips Semiconductors
Preliminary specication
5-band stereo equalizer circuit
TEA6360
I2C-BUS PROTOCOL
I2C-bus format
If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.
Byte organisation
Table 1 I2C-bus transmission
Function of the bits of Table 1:
S
SLAVE ADDRESS
A
SUBADDRESS
A
DATA
P
S
=
start condition
SLAVE ADDRESS
=
1000 0100 when pin 18 is set LOW
or 1000 0110 when pin 18 is set HIGH or open-circuit
A
=
acknowledge, generated by the slave
SUBADDRESS
=
subadress byte, see Table 1
DATA
=
data byte, see Table 1
P
=
stop condition
FUNCTION
SUBADDRESS BYTE
DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
lter 1/defeat
0
DEF
1B2
1B1
1B0
0
1C2
1C1
1C0
lter 2
0
1
0
2B2
2B1
2B0
0
2C2
2C1
2C0
lter 3
0
1
0
3B2
3B1
3B0
0
3C2
3C1
3C0
lter 4
0
1
0
4B2
4B1
4B0
0
4C2
4C1
4C0
lter 5
0
1
0
5B2
5B1
5B0
0
5C2
5C1
5C0
1B0
to
1B2
boost control for lter 1
1B0
to
1B2
cut control for lter 1
2B0
to
2B2
boost control for lter 2
2B0
to
2B2
cut control for lter 2
3B0
to
3B2
boost control for lter 3
3B0
to
3B2
cut control for lter 3
4B0
to
4B2
boost control for lter 4
4B0
to
4B2
cut control for lter 4
5B0
to
5B2
boost control for lter 5
5B0
to
5B2
cut control for lter 5
DEF
DEF = 0 (defeat bit):
All lters operating.
DEF = 1:
Linear frequency response, input is directly connected to the output of the
output amplier. The lter settings are stored but the internal amplication
is controlled to 0 dB, independent on bits nB2 to nB0.
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