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參數(shù)資料
| 型號(hào)： | 935041730623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | F/FAST SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 107K |
| 代理商： | 935041730623 |
Philips Semiconductors
Product specification
74F597
8-bit shift register with input storage registers
2
1991 Sep 13
853–1556 03964
FEATURES
High impedance PNP base inputs for reduced loading
(20
A in High and Low states)
8-bit parallel storage register
3-State output buffers
Shift register has asynchronous direct overriding reset
Shift load SHLD is functional when SHCP is Low and locked out
when SHCP is High
Guaranteed shift frequency DC to 105MHz
DESCRIPTION
The 74F597 consists of an 8-bit storage register feeding a
parallel-in/serial-in, serial-out 8-bit shift register. The storage register
and shift register have separate positive edge triggered clocks. The
shift register has asynchronous reset and when SHCP is Low, it has
asynchronous load.
The shift register load function has been modified to load when both
SHLD and SHCP are Low. When SHCP is High the shift register
load operation is not performed. Data will be properly shifted on the
rising edge of SHCP when SHLD is High.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
9
8
SF00366
D1
D2
D3
D4
D5
D6
D7
GND
VCC
D0
DS
SHLD
STCP
SHCP
SHRST
QS
TYPE
TYPICAL fMAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F597
135MHz
42mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
16-pin plastic DIP
N74F597N
SOT38-4
16-pin plastic SO
N74F597D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Ds
Serial data input
1.0/0.033
20
A/20A
D0–D7
Parallel data inputs
1.0/0.033
20
A/20A
SHCP
Shift register clock pulse input
1.0/0.033
20
A/20A
STCP
Storage register clock pulse input
1.0/0.033
20
A/20A
SHLD
Shift register load input (active Low)
1.0/0.033
20
A/20A
SHRST
Shift register reset input (active Low)
1.0/0.033
20
A/20A
Qs
Serial data output
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
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