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參數(shù)資料
| 型號： | 935030270602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 外設及接口 |
| 英文描述： | ADDR LATCH BASED PRPHL DRVR, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT38-4, DIP-16 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 123K |
| 代理商： | 935030270602 |
Philips Semiconductors
Product data
NE/SA5090
Addressable relay driver
2001 Aug 03
3
PIN DESIGNATION
PIN NO.
SYMBOL
NAME AND FUNCTION
1-3
A0-A2
A 3-bit binary address on these pins defines which of the 8 output latches is to receive the data.
4-7, 9-12
Q0-Q7
The 8 device outputs.
13
D
The data input. When the chip is enabled, this data bit is transferred to the defined output such that:
“1” turns output switch “ON”
“0” turns output switch “OFF”
14
CE
The chip enable. When this input is low, the output latches will accept data. When CE goes high, all
outputs will retain their existing state, regardless of address of data input condition.
15
CLR
The clear input. When CLR goes low all output switches are turned “OFF”. The high data input will
override the clear function on the addressed latch.
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
16-Pin Plastic Small Outline Large (SOL) Package
0
°C to +70 °C
NE5090D
SOT162–1
16-Pin Plastic Dual In-Line Package (DIP)
0
°C to +70 °C
NE5090N
SOT38–4
16-Pin Plastic Small Outline Large (SOL) Package
–40
°C to +85 °C
SA5090D
SOT162–1
16-Pin Plastic Dual In-Line Package (DIP)
–40
°C to +85 °C
SA5090N
SOT38–4
TRUTH TABLE
INPUTS
OUTPUTS
MODE
CLR
CE
D
A0
A1
A2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MODE
L
H
X
H
Clear
L
H
L
H
LLL
L
HH
HHH
HH
L
LL
H
L
H
HH
HHH
HH
Demultiplex
L
LH
HL
LH
L
H
HHH
HH
Demultiplex
L
HHH
H
HH
HHH
HH
L
HHHH
H
HH
HHH
H
L
H
X
QN-1
Memory
H
L
H
QN–1
H
L
H
LLL
L
QN–1
H
LL
H
L
QN–1
HQN–1
Addressable Latch
H
LH
HL
L
QN–1
LQN–1
Addressable Latch
H
L
HHH
QN–1
H
L
H
QN–1
L
NOTES:
X=Don’t care condition
QN-1=Previous output state
L=Low voltage level/“ON” output state
H=High voltage level/“OFF” output state
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