參數(shù)資料
型號(hào)： 935014090005
廠商： NXP SEMICONDUCTORS
元件分類： 顯示驅(qū)動(dòng)器
英文描述： LIQUID CRYSTAL DISPLAY DRIVER, UUC54
封裝： DIE-54
文件頁(yè)數(shù)： 11/46頁(yè)
文件大?。?/td> 287K
代理商： 935014090005
1998 Sep 08
19
Philips Semiconductors
Product specication
LCD row/column driver for dot matrix
graphic displays
PCF8578
8I2C-BUS PROTOCOL
Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8578 and PCF8579. The least
significant bit of the slave address is set by connecting
input SA0 to either 0 (VSS) or 1 (VDD). Therefore, two types
of PCF8578 or PCF8579 can be distinguished on the
same I2C-bus which allows:
1. One PCF8578 to operate with up to 32 PCF8579s on
the same I2C-bus for very large applications
2. The use of two types of LCD multiplex schemes on the
same I2C-bus.
In most applications the PCF8578 will have the same slave
address as the PCF8579.
The I2C-bus protocol is shown in Fig.13.
All communications are initiated with a start condition (S)
from the I2C-bus master, which is followed by the desired
slave address and read/write bit. All devices with this slave
address acknowledge in parallel. All other devices ignore
the bus transfer.
In WRITE mode (indicated by setting the read/write bit
LOW) one or more commands follow the slave address
acknowledgement. The commands are also
acknowledged by all addressed devices on the bus.
The last command must clear the continuation bit C.
After the last command a series of data bytes may follow.
The acknowledgement after each byte is made only by the
(A0, A1, A2 and A3) addressed PCF8579 or PCF8578
with its implicit subaddress 0. After the last data byte
has been acknowledged, the I2C-bus master issues a stop
condition (P).
In READ mode, indicated by setting the read/write bit
HIGH, data bytes may be read from the RAM following the
slave address acknowledgement. After this
acknowledgement the master transmitter becomes a
master receiver and the PCF8578 becomes a slave
transmitter. The master receiver must acknowledge the
reception of each byte in turn. The master receiver must
signal an end of data to the slave transmitter, by not
generating an acknowledge on the last byte clocked out of
the slave. The slave transmitter then leaves the data line
HIGH, enabling the master to generate a stop condition
(P).
Display bytes are written into, or read from, the RAM at the
address specified by the data pointer and subaddress
counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be
transferred either to, or from, the intended devices.
In multiple device applications, the hardware subaddress
pins of the PCF8579s (A0 to A3) are connected to VSS or
VDD to represent the desired hardware subaddress code.
If two or more devices share the same slave address, then
each device must be allocated a unique hardware
subaddress.
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