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參數(shù)資料
| 型號： | 935001480112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LCD CLOCK, PDSO40 |
| 封裝： | PLASTIC, SOT-158-2, VSOP-40 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 136K |
| 代理商： | 935001480112 |
1997 Apr 16
5
Philips Semiconductors
Product specication
4-digit LCD car clock
PCF1171C
Time correction
±2 minutes, switch S3
This switch operates in two ranges:
Displayed time ≥ 58 minutes 00 seconds
Displayed time ≤ 1 minute 59 seconds.
When switch S3 is pressed in these ranges, the minutes
and seconds are reset to zero. For displayed
time
≥ 58 minutes 00 seconds, the hour is also
incremented by one.
INPUT OPTIONS
In the description below S4, S5 and S6 refer to the external
switches shown in Fig.5 rather than to the corresponding
inputs.
In a real application, these inputs will normally be bonded
to the appropriate level to give the required function mode.
Internal/external regulation, switch S4
For internal regulation, S4 is closed, the internal voltage
regulator is active and the voltage supply for the LCD is
regulated to 5 V. For external regulation, S4 is open and
the circuit has to be supplied with an externally regulated
voltage.
12/24-hour mode, switch S5
For 12-hour display mode, S5 is connected to VDD.
For 24-hour display mode, S5 is connected to VSS.
Single/continuous correction mode, switch S6
For single-set correction mode, S6 is connected to VDD.
Each closure of S1 or S2 advances the counter by one.
For continuous-set correction mode, S6 is connected to
VSS. Momentary closure of S1 or S2 causes single
increments as for single-set correction mode. If S1 or S2 is
kept closed for more than 1s, the counter is automatically
incremented by 1 for each full second that S1 or S2 is kept
closed.
TESTING
In normal operation the test inputs TR (pin 38) and TS
(pin 39) have to be connected to VDD (pin 23). A test
frequency (64 Hz) is available at BP (pin 5). The test mode
is activated by connecting TS to VSS (pin 20). All output
frequencies are then increased by a factor of 65536.
In this mode the maximum input frequency is 100 kHz
(external generator at OSC IN). By connecting TR to VSS
all counters (seconds, minutes and hours) are stopped.
After connecting TR to VDD all counters start from an initial
state.
The switches/inputs described above also operate in the
test mode.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. Connecting the supply voltage with reverse polarity, will not harm the circuit, provided the current is limited to 10 mA
by the external resistor.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
advisable to take handling precautions appropriate to handling MOS devices. Advice can be found in
“Data Handbook IC16, General, Handling MOS Devices”.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage with respect to VSS with internal
regulation disconnected;
note 1
8V
VI
all input voltages
VSS 0.3
VDD + 0.3
V
Tamb
operating ambient temperature
40
+85
°C
Tstg
storage temperature
55
+125
°C
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