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參數(shù)資料
| 型號： | 933825570005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | HC/UH SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 41K |
| 代理商： | 933825570005 |
December 1990
2
Philips Semiconductors
Product specication
Quad buffer/line driver; 3-state
74HC/HCT125
FEATURES
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT125 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled
by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a HIGH impedance OFF-state.
The “125” is identical to the “126” but has active LOW enable inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay nA to nY
CL = 15 pF; VCC =5V
9
12
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per buffer
notes 1 and 2
22
24
pF
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