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參數(shù)資料
| 型號(hào)： | 933795190602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | F/FAST SERIES, 16-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001AF, SOT-222-1, DIP-24 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 97K |
| 代理商： | 933795190602 |
Philips Semiconductors
Product specification
74F676
16-bit serial/parallel-in, serial-out shift register (3-State)
2
1990 Apr 18
853–0284 99394
FEATURES
16-bit parallel-to-serial conversion
16-bit serial-in, serial-out
Chip select control
Power supply current 48mA typical
Shift frequency 110MHz tyical
Available in 300mil-wide 24-pin Slim DIP package
DESCRIPTION
The 74F676 contains 16 flip-flops with provision for synchronous
parallel or serial entry and serial output. When the mode (M) input is
High, information present on the parallel data (D0–D15) inputs is
entered on the falling edge of the clock pulse (CP) input signal.
When M is Low, data is shifted out of the most significant bit position
while information present on the serial (SI) input shifts into the least
significant bit position. A High signal on the chip select (CS) input
prevents both parallel and serial operations.
The 16 bit shift register operates in one of three modes, as indicated
in the shift register Function Table.
Hold: A High signal on the Chip Select (CS) input prevents clocking
and data is stored in the 16 registers.
Serial load: Data present on the SI pin shifts into the register on the
falling edge of CP. Data enters the Q0 position and shifts toward
Q15 on successive clocks finally appearing on the SO pin.
Parallel load: Data present on D0–D15 is entered into the register
on the falling edge of CP. The SO output represents the Q15 register
output.
To prevent false clocking, CP must be Low during a Low-to-High
transition of CS.
PIN CONFIGURATION
24
1
VCC
CS
23
22
21
20
19
18
17
16
10
15
9
8
7
6
5
4
3
2
D15
D14
D11
D10
D9
D8
CP
M
SO
D1
D2
D3
D13
D12
NC
SI
SF01209
D0
D7
14
12
13
11
D6
D4
GND
D5
TYPE
TYPICAL fMAX
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F676
110MHz
48mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
24-Pin Plastic Slim
DIP (300mil)
N74F676N
SOT222-1
24-Pin Plastic SOL
N74F676D
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0–D15
Parallel data inputs
1.0/1.0
20
A/0.6mA
SI
Serial data input
1.0/1.0
20
A/0.6mA
CS
Chip Select input (active Low)
1.0/1.0
20
A/0.6mA
CP
Clock Pulse input (active falling edge)
1.0/1.0
20
A/0.6mA
M
Mode select input
1.0/1.0
20
A/0.6mA
SO
Serial data output
50/33
1mA/20mA
NOTE: One (1.0) FAST Unit Load is defined as: 20
A in the High state and 0.6mA in the Low state.
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