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參數(shù)資料
| 型號(hào)： | 933794830602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | F/FAST SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001AF, SOT-222-1, DIP-24 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | 933794830602 |
Philips Semiconductors
Product specification
74F198
8-bit bidirectional universal shift register
2
October 2, 1987
853–0089 90746
FEATURES
Buffered clock and control inputs
Shift right, shift left, and parallel load capability
Asynchronous Master Reset
DESCRIPTION
The 74F198 Bidirectional Universal Shift Register is designed to
incorporate virtually all of the features a system designer may want
in a shift register. This circuit features parallel inputs and outputs,
shift right and shift left serial inputs, operating mode select inputs,
and direct overriding master reset input. The register has four
distinct modes of operation:
– Parallel (broadside) load
– Shift right (in the direction Q0 toward Q7)
– Shift left (in the direction Q7 toward Q0)
– Inhibit clock (do nothing).
Synchronous parallel loading is accomplished by applying the 8 bits
of data and taking both mode control inputs, S0 and S1, High. The
data is loaded into the associated flip-flop and appears at the
outputs after the positive transition of the clock inputs. During
loading, serial data flow is inhibited.
Shift right is accomplished synchronously, with the rising edge of the
clock pulse when S0 is High and S1 is Low. Serial data for this
mode is entered at the right data input (DSR). When S0 is Low and
S1 is High, data shifts left synchronously and new data is entered at
the shift-left serial input (DSL).
Clocking of the flip-flops is inhibited when both mode control inputs
are Low.
PIN CONFIGURATION
SF00160
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S0
DSR
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CP
VCC
S1
DSL
D7
Q7
D6
Q6
Q5
D5
D4
Q4
MR
GND
TYPE
TYPICAL fMAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F198
95MHz
73mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
24-pin Plastic Slim
DIP (300mil)
N74F198N
SOT222-1
24-pin Plastic SOL
N74F198D
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
D0–D7
Parallel data inputs
1.0/1.0
20
A/0.6mA
DSR
Serial data input (Shift Right)
1.0/1.0
20
A/0.6mA
DSL
Serial data input (Shift Left)
1.0/1.0
20
A/0.6mA
S0–S1
Mode Select inputs
1.0/1.0
20
A/0.6mA
CP
Clock Pulse input (Active rising edge)
1.0/1.0
20
A/0.6mA
MR
Master Reset input (Active Low)
1.0/1.0
20
A/0.6mA
Q0–Q7
Data outputs
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
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