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參數(shù)資料
| 型號： | 933779080623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 933779080623 |
Philips Semiconductors
Product specification
74F259
Latch
1989 Apr 11
6
AC ELECTRICAL CHARACTERISTICS
LIMITS
Tamb = +25°C
Tamb = 0°C to +70°C
SYMBOL
PARAMETER
TEST
VCC = +5V
VCC = +5V ± 10%
UNIT
CONDITION
CL = 50pF, RL = 500
MIN
TYP
MAX
MIN
MAX
tPLH
tPHL
Propagation delay
D to Qn
Waveform
NO TAG
4.0
3.0
7.0
5.0
9.0
7.0
4.0
2.5
10.0
7.5
ns
tPLH
tPHL
Propagation delay
E to Qn
Waveform
NO TAG
4.5
3.0
8.0
5.0
10.5
7.0
4.5
3.0
12.0
8.0
ns
tPLH
tPHL
Propagation delay
An to Qn
Waveform
NO TAG
5.0
4.0
10.0
8.5
14.0
9.5
5.0
4.0
14.5
10.0
ns
tPHL
Propagation delay
MR to Qn
Waveform
NO TAG
5.0
7.0
9.0
4.5
10.0
ns
AC SETUP REQUIREMENTS
LIMITS
Tamb = +25°C
Tamb = 0°C to +70°C
SYMBOL
PARAMETER
TEST
VCC = +5.0V
VCC = +5.0V ± 10%
UNIT
CONDITION
CL = 50pF, RL = 500
CL= 50pF, RL = 500
MIN
TYP
MAX
MIN
MAX
ts(H)
ts(L)
Setup time, High or Low
D to E
Waveform
NO TAG
3.0
6.5
3.0
7.0
ns
th(H)
th(L)
Hold time, High or Low
D to E
Waveform
NO TAG
0
ns
ts(H)
ts(L)
Setup time, High or Low
An to E1
Waveform
NO TAG
2.0
ns
th(H)
th(L)
Hold time, High or Low
An to E2
Waveform
NO TAG
0
ns
tw(L)
E Pulse width, Low
Waveform
NO TAG
7.5
8.0
ns
tw(L)
MR Pulse width, Low
Waveform
NO TAG
3.0
ns
NOTES:
1. The Address to Enable setup time is the time before the High-to-Low Enable transition that the Address must be stable so that the correct
latch is addressed and the other latches are not affected.
2. The Address to Enable hold time is the time before the Low-to-High Enable transition that the Address must be stable so that the correct
latch is addressed and the other latches are not affected.
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