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參數(shù)資料
| 型號： | 933757290652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 算術(shù)邏輯單元 |
| 英文描述： | HC/UH SERIES, 4-BIT ADDER/SUBTRACTOR, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 59K |
| 代理商： | 933757290652 |
December 1990
6
Philips Semiconductors
Product specication
4-bit binary full adder with fast carry
74HC/HCT283
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CIN to ∑1
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
CIN to ∑2
58
21
17
180
36
31
225
45
38
270
54
46
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
CIN to ∑3
63
23
18
195
39
33
245
49
42
295
59
50
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
CIN to ∑4
74
27
22
230
46
39
290
58
49
345
69
59
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
An or Bn to ∑n
69
25
20
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
CIN to COUT
63
23
18
195
39
33
245
49
42
295
59
50
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
An or Bn to COUT
63
23
18
195
39
33
245
49
42
295
59
50
ns
2.0
4.5
6.0
Fig.6
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
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