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參數(shù)資料
| 型號： | 933756960112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 43K |
| 代理商： | 933756960112 |
December 1990
5
Philips Semiconductors
Product specication
4-bit binary ripple counter
74HC/HCT93
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP0 to Q0
41
15
12
125
25
21
155
31
26
190
38
32
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
CP1 to Q1
49
16
13
135
27
23
170
34
29
205
41
35
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
CP1 to Q2
61
22
18
185
37
31
230
46
39
280
56
48
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
CP1 to Q3
80
29
23
245
49
42
305
61
52
370
71
63
ns
2.0
4.5
6.0
Fig.6
tPHL
propagation delay
MRn to Qn
50
18
14
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.7
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
trem
removal time
MRn to CP0, CP1
50
10
9
8
3
2
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.7
tW
pulse width
CP0, CP1
80
16
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
tW
master reset pulse width
MRn
80
16
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
fmax
maximum clock pulse
frequency
CP0, CP1
6.0
30
35
30
91
108
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6
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| 0560-6600-62 | TELECOM TRANSFORMER |
| 933825550005 | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, UUC |
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| 935187290112 | HC/UH SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14 |
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