參數(shù)資料
型號(hào): 933738320118
廠商: NXP SEMICONDUCTORS
元件分類: 外設(shè)及接口
英文描述: ADDR LATCH BASED PRPHL DRVR, PDSO16
封裝: 7.50 MM, PLASTIC, SOT162-1, MS-013, SO-16
文件頁數(shù): 6/10頁
文件大小: 123K
代理商: 933738320118
Philips Semiconductors
Product data
NE/SA5090
Addressable relay driver
2001 Aug 03
5
SWITCHING CHARACTERISTICS
VCC = 5 V; Tamb = 25 °C; VOUT = 5 V; IOUT = 100 mA; VIL = 0.8 V; VIH = 2.0 V.
SYMBOL
PARAMETER
TO
FROM
MIN
TYP
MAX
UNIT
Propagation delay time
tPLH
Low-to-high1
Output
CE
900
1800
ns
tPHL
High-to-low1
130
260
tPLH
Low-to-high2
Output
Data
920
1850
ns
tPHL
High-to-low2
Output
Data
130
260
ns
tPLH
Low-to-high3
Output
Address
900
1800
ns
tPHL
High-to-low3
Output
Address
130
260
ns
tPLH
Low-to-high4
Output
CLR
920
1850
ns
tPHL
High-to-low4
Output
CLR
ns
Switching setup requirements
tS( )
Set-up time HIGH
Chip enable
High data
40
ns
tS(H)
Set-up time LOW
Chip enable
Low data
50
ns
tS(A)
Address set-up time
Chip enable
Address
40
ns
t ()
Hold time HIGH
Chip enable
High data
10
ns
tH(H)
Hold time LOW
Chip enable
Low data
10
ns
tPW(E)
Chip enable pulse width1
40
ns
NOTES:
1. See Turn-On and Turn-Off Delays, Enable-to-Output and Enable Pulse Width timing diagram.
2. See Turn-On and Turn-Off Delays, Data-to-Output timing diagram.
3. See Turn-On and Turn-Off Delays, Address-to-Output timing diagram.
4. See Turn-Off Delay, Clear-to-Output timing diagram.
5. See Set-up and Hold Time, Data-to-Enable timing diagram.
6. See Set-up Time, Address-to-Enable timing diagram.
FUNCTIONAL DESCRIPTION
This peripheral driver has latched outputs which hold the input date
until cleared. The NE5090 has active-LOW, open-collector outputs,
all of which are cleared when power is first applied. This device is
identical to the NE590, except the outputs can withstand 28 V.
Addressable Latch Function
Any given output can be turned on or off by presenting the address
of the output to be set or cleared to the three address pins, by
holding the “D” input High to turn on the selected output, or by
holding it Low to turn off, holding the CLR input High, and bringing
the CE input Low. Once an output is turned on or off, it will remain
so until addressed again, or until all outputs are cleared by bringing
the CLR input Low while holding the CE input High.
Demultiplexer Operation
By holding the CLR and CE inputs Low and the ”D“ input High, the
addressed output will remain on and all other outputs will be off.
High Current Outputs
The obvious advantage of this device over other drivers such as the
9334 and N74LS259 is the fact that the outputs of the NE5090 are
each capable of 200 mA and 28 V. It must be noted, however, that
the total power dissipation would be over 2.5 W if all 8 outputs were
on together and carrying 200 mA each. Since the total power
dissipation is limited by the package to 1 W, and since power
dissipation due to supply current is 0.25 W, the total load power
dissipation by the device is limited to 0.75 W at room temperature,
and decreases as ambient temperature rises.
The maximum die junction temperature must be limited to 165
°C,
and the temperature rise above ambient and the junction
temperature are defined as:
TR = θJA × PD
Tj = Tamb +tR
For example, if we are using the NE5090 in a plastic package in an
application where the ambient temperature is never expected to rise
above 50
°C, and the output current at the 8 outputs, when on, are
100, 40, 50, 200, 15, 30, 80, and 10 mA, we find from the graph of
output voltage vs load current that the output voltages are expected
to be about 0.92, 0.75, 0.78, 1.04, 0.5, 0.7, 0.9, and 0.4 V,
respectively. Total device power due to these loads is found to be
473.5 mW. Adding the 200 mW due to the power supply brings total
device power dissipation to 723.5 mW. The thermal resistances are
83
°C per W for plastic packages. Using the equations above we
find:
Plastic TR=83×0.7235=60°C
Plastic TJ =50+60=100°C
Thus we find that TJ is below the 165 °C maximum, and either
package could be used in this application. The graphs of total load
power versus ambient temperature would also give us this same
information, although interpreting the graphs would not yield the
same accuracy.
相關(guān)PDF資料
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933738320602 ADDR LATCH BASED PRPHL DRVR, PDSO16
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