參數(shù)資料
型號(hào)： 933715420653
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
封裝： PLASTIC, SO-16
文件頁數(shù)： 5/7頁
文件大?。?/td> 55K
代理商： 933715420653
December 1990
5
Philips Semiconductors
Product specication
Quad bistable transparent latch
74HC/HCT75
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL =50pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to+85
40 to+125
min.
typ.
max. min. max. min.
max.
tPHL/ tPLH
propagation delay
nD to nQ
33
12
10
110
22
19
140
28
24
165
33
28
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
nD to nQ
39
14
11
120
24
20
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.7
tPHL/ tPLH
propagation delay
LEn-n to nQ
33
12
10
120
24
20
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.8
tPHL/ tPLH
propagation delay
LEn-n to nQ
39
14
11
125
25
21
155
31
26
190
38
32
ns
2.0
4.5
6.0
Fig.8
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 6 and 7
tW
enable pulse width
HIGH
80
16
14
17
6
5
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
tsu
set-up time
nD to LEn-n
60
12
10
14
5
4
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.9
th
hold time
nD to LEn-n
3
8
3
2
3
ns
2.0
4.5
6.0
Fig.9
相關(guān)PDF資料
PDF描述
935190280112 HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
933669870652 HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16
935190280118 HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
935188770112 HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
933824850005 HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, UUC
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