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參數(shù)資料
| 型號： | 933714630652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 諧振器 |
| 英文描述： | HC/UH SERIES, DUAL MONOSTABLE MULTIVIBRATOR, PDSO16 |
| 封裝： | SOT-109, SO-16 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 332K |
| 代理商： | 933714630652 |
December 1990
2
Philips Semiconductors
Product specication
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
FEATURES
Pulse width variance is typically less than ± 5%
Pin-out identical to “123”
Overriding reset terminates output pulse
nB inputs have hysteresis for improved noise immunity
Output capability: standard (except for nREXT/CEXT)
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT221 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT221 are dual non-retriggerable monostable
multivibrators. Each multivibrator features an active
LOW-going edge input (nA) and an active HIGH-going
edge input (nB), either of which can be used as an enable
input.
Pulse triggering occurs at a particular voltage level and is
not directly related to the transition time of the input pulse.
Schmitt-trigger input circuitry for the nB inputs allow
jitter-free triggering from inputs with slow transition rates,
providing the circuit with excellent noise immunity.
Once triggered, the outputs (nQ, nQ) are independent of
further transitions of nA and nB inputs and are a function
of the timing components. The output pulses can be
terminated by the overriding active LOW reset inputs
(nRD). Input pulses may be of any duration relative to the
output pulse.
Pulse width stability is achieved through internal
compensation and is virtually independent of VCC and
temperature. In most applications pulse stability will only
be limited by the accuracy of the external timing
components.
The output pulse width is defined by the following
relationship:
tW =CEXTREXTIn2
tW = 0.7CEXTREXT
Pin assignments for the “221” are identical to those of the
“123” so that the “221” can be substituted for those
products in systems not using the retrigger by merely
changing the value of REXT and/or CEXT.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) + 0.33 × CEXT × VCC2 × fo + D × 28 × VCC where:
fi = input frequency in MHz; fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CEXT = timing capacitance in pF; CL = output load capacitance in pF
VCC = supply voltage in V; D = duty factor in %
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
propagation delay
CL = 15 pF; VCC =5 V;
REXT =5 k; CEXT = 0 pF
tPHL
nA, nB, nRD to nQ, nQ
2932ns
tPLH
nA, nB, nRD to nQ, nQ
3536ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package notes 1 and 2
90
96
pF
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