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參數資料
| 型號： | 933714550652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數移位寄存器 |
| 英文描述： | HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOT-109-1, SO-16 |
| 文件頁數： | 3/10頁 |
| 文件大?。?/td> | 90K |
| 代理商： | 933714550652 |
December 1990
2
Philips Semiconductors
Product specication
8-bit parallel-in/serial-out shift register
74HC/HCT166
FEATURES
Synchronous parallel-to-serial applications
Synchronous serial data input for easy expansion
Clock enable for “do nothing” mode
Asynchronous master reset
For asynchronous parallel data load see “165”
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT166 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT166 are 8-bit shift registers which have a
fully synchronous serial or parallel data entry selected by
an active LOW parallel enable (PE) input. When PE is
LOW one set-up time prior to the LOW-to-HIGH clock
transition, parallel data is entered into the register. When
PE is HIGH, data is entered into the internal bit position Q0
from serial data input (Ds), and the remaining bits are
shifted one place to the right (Q0 → Q1 → Q2, etc.) with
each positive-going clock transition.
This feature allows parallel-to-serial converter expansion
by tying the Q7 output to the Ds input of the succeeding
stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take place
while CP is HIGH for predictable operation. A LOW on the
master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all bit positions
to a LOW state.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CP to Q7
MR to Q7
CL = 15 pF; VCC =5 V
15
14
20
19
ns
fmax
maximum clock frequency
63
50
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
41
pF
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