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參數(shù)資料
| 型號： | 933714510653 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16 |
| 封裝： | SOT-109, SO-16 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 147K |
| 代理商： | 933714510653 |
December 1990
6
Philips Semiconductors
Product specication
Presettable synchronous BCD decade
counter; asynchronous reset
74HC/HCT160
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min. typ.
max.
min.
max.
min.
max.
tPHL/ tPLH propagation delay
CP to Qn
61
22
18
185
37
31
230
46
39
280
56
48
ns
2.0
4.5
6.0
Fig. 8
tPHL/ tPLH propagation delay
CP to TC
69
25
20
215
43
31
270
54
46
325
65
55
ns
2.0
4.5
6.0
Fig. 8
tPHL
propagation delay
MR to Qn
69
25
20
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig. 9
tPHL
propagation delay
MR to TC
69
25
20
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig. 9
tPHL/ tPLH propagation delay
CET to TC
47
17
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig. 10
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 8 and 10
tW
clock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig. 8
tW
master reset pulse width
LOW
80
16
14
28
10
8
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig. 9
trem
removal time
MR to CP
100
20
17
30
11
9
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig. 9
tsu
set-up time
Dn to CP
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig. 11
tsu
set-up time
PE to CP
135
27
23
41
15
12
170
34
29
205
41
35
ns
2.0
4.5
6.0
Fig. 11
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