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參數(shù)資料
| 型號： | 933714490652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 933714490652 |
1998 Jun 10
6
Philips Semiconductors
Product specication
Dual JK ip-op with set and reset;
negative-edge trigger
74HC/HCT112
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
TEST CONDITIONS
74HC
UNIT
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
nCP to nQ
55
175
220
265
ns
2.0
Fig.6
20
35
44
53
4.5
16
30
37
45
6.0
tPHL/ tPLH
propagation delay
nCP to nQ
55
175
220
265
ns
2.0
Fig.6
20
35
44
53
4.5
16
30
37
45
6.0
tPHL/ tPLH
propagation delay
nRD to nQ, nQ
58
180
225
270
ns
2.0
Fig.7
21
36
45
54
4.5
17
31
38
46
6.0
tPHL/ tPLH
propagation delay
nSD to nQ, nQ
50
155
295
235
ns
2.0
Fig.7
18
31
39
47
4.5
14
26
33
40
6.0
tTHL/ tTLH
output transition time
19
75
95
110
ns
2.0
Fig.6
7
15
19
22
4.5
6
13
16
19
6.0
tW
clock pulse width
HIGH or LOW
80
22
100
120
ns
2.0
Fig.6
16
8
20
24
4.5
14
6
17
20
6.0
tW
set or reset pulse width
LOW
80
22
100
120
ns
2.0
Fig.7
16
8
20
24
4.5
14
6
17
20
6.0
trem
removal time
nRD to nCP
80
22
125
150
ns
2.0
Fig.7
16
8
25
30
4.5
14
6
21
26
6.0
trem
removal time
nSD to nCP
80
19
100
120
ns
2.0
Fig.7
16
7
20
24
4.5
14
6
17
20
6.0
tsu
set-up time
nJ, nK to nCP
80
19
100
120
ns
2.0
Fig.6
16
7
20
24
4.5
14
6
17
20
6.0
th
hold time
nJ, nK to nCP
0
11
0
ns
2.0
Fig.6
0
4
0
4.5
0
3
0
6.0
fmax
maximum clock pulse
frequency
6
20
4.8
4.0
MHz
2.0
Fig.6
30
60
24
20
4.5
35
71
28
24
6.0
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