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參數(shù)資料
| 型號(hào)： | 933714070652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14 |
| 封裝： | SOT-108-1, SO-14 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 52K |
| 代理商： | 933714070652 |
December 1990
2
Philips Semiconductors
Product specication
8-bit serial-in/parallel-out shift register
74HC/HCT164
FEATURES
Gated serial data inputs
Asynchronous master reset
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT164 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT164 are 8-bit edge-triggered shift registers
with serial data entry and an output from each of the eight
stages.
Data is entered serially through one of two inputs (Dsa or
Dsb); either input can be used as an active HIGH enable for
data entry through the other input.
Both inputs must be connected together or an unused
input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH
transition of the clock (CP) input and enters into Q0, which
is the logical AND of the two data inputs (Dsa,Dsb) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all
other inputs and clears the register asynchronously,
forcing all outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CP to Qn
MR to Qn
CL = 15 pF; VCC = 5 V
12
11
14
16
ns
fmax
maximum clock frequency
78
61
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per
package
notes 1 and 2
40
pF
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