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參數(shù)資料
| 型號： | 933713680118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | HC/UH SERIES, QUAD 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO14 |
| 封裝： | PLASTIC, SO-14 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 49K |
| 代理商： | 933713680118 |
December 1990
2
Philips Semiconductors
Product specication
Quad bus transceiver; 3-state
74HC/HCT243
FEATURES
Non-inverting 3-state outputs
2-way asynchronous data bus communication
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT243 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT243 are quad bus transceivers featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions.
They are designed for 4-line asynchronous 2-way data
communications between data buses.
The output enable inputs (OEA and OEB) can be used to
isolate the buses.
The “243” is similar to the “242” but has non-inverting (true)
outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
An to Bn;
Bn to An
CL = 15 pF; VCC = 5 V
6
11
ns
CI
input capacitance
3.5
pF
CI/O
input/output capacitance
10
pF
CPD
power dissipation capacitance per transceiver notes 1 and 2
26
34
pF
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