參數(shù)資料
型號(hào)： 933713390653
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14
文件頁(yè)數(shù)： 14/18頁(yè)
文件大?。?/td> 178K
代理商： 933713390653
1998 Feb 23
5
Philips Semiconductors
Product specication
Dual D-type ip-op with set and reset;
positive-edge trigger
74HC/HCT74
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max. min.
max
min.
max.
tPHL/ tPLH propagation delay
nCP to nQ, nQ
47
175
220
265
ns
2.0
Fig.6
17
35
44
53
4.5
14
30
37
45
6.0
tPHL/ tPLH propagation delay
nSD to nQ, nQ
50
200
250
300
ns
2.0
Fig.7
18
40
50
60
4.5
14
34
43
51
6.0
tPHL/ tPLH propagation delay
nRD to nQ, nQ
52
200
250
300
ns
2.0
Fig.7
19
40
50
60
4.5
15
34
43
51
6.0
tTHL/ tTLH
output transition time
19
75
95
110
ns
2.0
Fig.6
7
15
19
22
4.5
6
13
16
19
6.0
tW
clock pulse width
HIGH or LOW
80
19
100
120
ns
2.0
Fig.6
16
7
20
24
4.5
14
6
17
20
6.0
tW
set or reset pulse width
LOW
80
19
100
120
ns
2.0
Fig.7
16
7
20
24
4.5
14
6
17
20
6.0
trem
removal time
set or reset
30
3
40
45
ns
2.0
Fig.7
6
1
8
9
4.5
5
1
7
8
6.0
tsu
set-up time
nD to nCP
60
6
75
90
ns
2.0
Fig.6
12
2
15
18
4.5
10
2
13
15
6.0
th
hold time
nCP to nD
3
6
3
ns
2.0
Fig.6
3
2
3
4.5
3
2
3
6.0
fmax
maximum clock pulse
frequency
6.0
23
4.8
4.0
MHz
2.0
Fig.6
30
69
24
20
4.5
35
82
28
24
6.0
相關(guān)PDF資料
PDF描述
935175170112 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935175170118 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935175180118 HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
933669130652 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
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