參數(shù)資料
型號: 933711390602
廠商: NXP SEMICONDUCTORS
元件分類: 總線收發(fā)器
英文描述: F/FAST SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDIP20
封裝: 0.300 INCH, PLASTIC, SOT-146-1, DIP-20
文件頁數(shù): 5/12頁
文件大?。?/td> 94K
代理商: 933711390602
Philips Semiconductors
Product specification
74F244/74F244B
Octal buffers (3-State)
2
1994 Dec 5
853-0357 14381
FEATURES
Octal bus interface
3-State output buffer sink 64mA
15mA source current
Guaranteed output skew less than 2.0ns (74F244B)
Reduced ground bounce (74F244B)
Reduced I
CC (74F244B)
Reduced loading (74F244B I
IL = 40A)
Split lead frame offers increased noise immunity (74F244B)
Industrial temperature range available (-40°C to +85°C) for
74F244
74F244 available in SSOP Type II package
DESCRIPTION
The 74F244 is an octal buffer that is ideal for driving bus lines of
buffer memory address registers. The outputs are all capable of
sinking 64mA and sourcing up to 15mA, producing very good
capacitive drive characteristics. The device features two output
enables, OEa and OEb, each controlling four of the 3-State outputs.
The 74F244B is functionally equivalent to the 74F244. It has been
designed to reduce effects of ground noise. Other advantages are
noted in the features.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT (TOTAL)
74F244
4.0ns
53mA
74F244B
4.0ns
33mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
INDUSTRIAL RANGE
PKG DWG #
DESCRIPTION
VCC = 5V ±10%,
PKG DWG #
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
20-pin plastic DIP
N74F244N, N74F244BN
I74F244N
SOT146-1
20-pin plastic SOL
N74F244D, N74F244BD
I74F244D
SOT163-1
20-pin plastic SSOP II
N74F244DB
SOT339-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Ian, Ibn
Data inputs (74F244)
1.0/2.67
20
A/1.6mA
Data inputs (74F244B)
1.0/0.067
20
A/40A
OEa, OEb
Output enable inputs (active low) (74F244)
1.0/1.67
20
A/1.0mA
Output enable inputs (active low) (74F244B)
1.0/0.067
20
A/40A
Yan, Ybn
Data outputs
750/106.7
15mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 VCC
OEa
Ia0
Yb0
Ia1
Yb1
Ia2
Yb2
Ia3
Yb3
GND
SF00227
OEb
Ya0
Ib0
Ya1
Ib1
Ya2
Ib2
Ya3
Ib3
LOGIC SYMBOL
OEa
1
SF00228
2
4
6
8
17
15
13
11
18
16
14
12
3
5
7
9
Ia0
Ia1
Ia2
Ia3
Ib0
Ib1
Ib2
Ib3
Ya0
Ya1 Ya2
Ya3 Yb0 Yb1 Yb2 Yb3
VCC = Pin 20
GND = Pin 10
OEb
19
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