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參數(shù)資料
| 型號(hào)： | 933669700652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDIP16 |
| 封裝： | PLASTIC, SOT38-1, DIP-16 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 46K |
| 代理商： | 933669700652 |
December 1990
6
Philips Semiconductors
Product specication
12-stage binary ripple counter
74HC/HCT4040
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (
ICC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
CP
MR
0.85
1.10
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Q0
19
40
50
60
ns
4.5
Fig.7
tPHL/ tPLH
propagation delay
Qn to Qn+1
10
20
25
30
ns
4.5
Fig.7
tPHL
propagation delay
MR to Qn
23
45
56
68
ns
4.5
Fig.7
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.7
tW
clock pulse width
HIGH or LOW
16
7
20
24
ns
4.5
Fig.7
tW
master reset pulse
width; HIGH
16
6
20
24
ns
4.5
Fig.7
trem
removal time
MR to CP
10
2
13
15
ns
4.5
Fig.7
fmax
maximum clock pulse
frequency
30
72
24
20
MHz
4.5
Fig.7
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