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參數(shù)資料
| 型號： | 933669680652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 83K |
| 代理商： | 933669680652 |
December 1990
7
Philips Semiconductors
Product specication
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to+85
40 to+125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP0 to Qn
63
23
18
230
46
39
290
58
49
345
69
59
ns
2.0
4.5
6.0
Fig.9
tPHL/ tPLH
propagation delay
CP0 to Q5-9
63
23
18
230
46
39
290
58
49
345
69
59
ns
2.0
4.5
6.0
Fig.9
tPHL/ tPLH
propagation delay
CP1 to Qn
61
22
18
250
50
43
315
63
54
375
75
64
ns
2.0
4.5
6.0
Fig.9
tPHL/ tPLH
propagation delay
CP1 to Q5-9
61
22
18
250
50
43
315
63
54
375
75
64
ns
2.0
4.5
6.0
Fig.9
tPHL
propagation delay
MR to Q19
52
19
15
230
46
39
290
58
49
345
69
59
ns
2.0
4.5
6.0
Fig.8
tPLH
propagation delay
MR to Q59, Q0
55
20
16
230
46
39
290
58
49
345
69
59
ns
2.0
4.5
6.0
Fig.8
tTHL/ tTLH
output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.9
tW
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
tW
master reset pulse
width; HIGH
80
16
14
19
7
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
trem
removal time
MR to CP0, CP1
5
17
6
5
ns
2.0
4.5
6.0
Fig.8
tsu
set-up time
CP1 to CP0;
CP0 to CP1
50
10
9
8
3
2
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.7
th
hold time
CP0 to CP1;
CP1 to CP0
50
10
9
17
6
5
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.7
fmax
maximum clock
pulse frequency
6.0
30
25
23
70
83
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.8
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