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參數(shù)資料
| 型號(hào)： | 933669670652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | HC/UH SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | SOT-38-1, DIP-16 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大小： | 49K |
| 代理商： | 933669670652 |
December 1990
2
Philips Semiconductors
Product specication
Dual 4-bit serial-in/parallel-out shift
register
74HC/HCT4015
FEATURES
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4015 are high-speed Si-gate CMOS
devices and are pin compatible with the “4015” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4015 are dual edge-triggered 4-bit static
shift registers (serial-to-parallel converters). Each shift
register has a serial data input (1D and 2D), a clock input
(1CP and 2CP), four fully buffered parallel outputs (1Q0 to
1Q3 and 2Q0 to 2Q3) and an overriding asynchronous
master reset (1MR and 2MR). Information present on nD
is shifted to the first register position, and all data in the
register is shifted one position to the right on the
LOW-to-HIGH transition of nCP.
A HIGH on nMR clears the register and forces nQ0 to nQ3
to LOW, independent of nCP and nD.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay nCP to nQn
CL = 15 pF; VCC = 5 V 1618ns
fmax
maximum clock frequency
110
74
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per register
notes 1 and 2
35
40
pF
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