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參數(shù)資料
| 型號(hào)： | 933669440652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MO-001AE, SOT-38-1, DIP-16 |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大小： | 183K |
| 代理商： | 933669440652 |
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1998 Jul 08
6
Philips Semiconductors
Product specication
Quad D-type ip-op with reset; positive-edge trigger
74HC/HCT175
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
MR
1.00
CP
0.60
Dn
0.40
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn, Qn
19
33
41
50
ns
4.5
Fig.6
tPHL
propagation delay
MR to Qn
22
38
48
57
ns
4.5
Fig.8
tPLH
propagation delay
MR to Qn
19
35
44
53
ns
4.5
Fig.8
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.6
tW
clock pulse width
HIGH or LOW
20
12
25
30
ns
4.5
Fig.6
tW
master reset pulse width
LOW
20
11
25
30
ns
4.5
Fig.8
trem
removal time
MR to CP
5
10
5
ns
4.5
Fig.8
tsu
set-up time
Dn to CP
16
5
20
24
ns
4.5
Fig.7
th
hold time
CP to Dn
5
0
5
ns
4.5
Fig.7
fmax
maximum clock pulse
frequency
25
49
20
17
MHz
4.5
Fig.6
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