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參數(shù)資料
| 型號： | 933668140602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, MO-001AA, SOT-27-1, DIP-14 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 90K |
| 代理商： | 933668140602 |
Philips Semiconductors
Product specification
74F74
Dual D-type flip-flop
2
1996 Mar 12
853 0335 16554
FEATURE
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F74 is a dual positive edge-triggered D-type flip-flop featuring
individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input. When
set and reset are inactive (high), data at the D input is transferred to
the Q and Q outputs on the low-to-high transition of the clock. Data
must be stable just one setup time prior to the low-to-high transition of
the clock for predictable operation. Clock triggering occurs at a
voltage level and is not directly related to the transition time of the
positive-going pulse. Following the hold time interval, data at the D
input may be changed without affecting the levels of the output.
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
SD1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
SD0
Q0
SF00045
TYPE
TYPICAL fmax
TYPICAL SUPPLY CURRENT (TOTAL)
74F74
125MHz
11.5mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%,
Tamb = –40°C to +85°C
PKG. DWG. #
14-pin plastic DIP
N74F74N
I74F74N
SOT27-1
14-pin plastic SO
N74F74D
I74F74D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
D0, D1
Data inputs
1.0/1.0
20
A/0.6mA
CP0, CP1
Clock inputs (active rising edge)
1.0/1.0
20
A/0.6mA
SD0, SD1
Set inputs (active low)
1.0/3.0
20
A/1.8mA
RD0, RD1
Reset inputs (active low)
1.0/3.0
20
A/1.8mA
Q0, Q1, Q0, Q1
Data outputs
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
LOGIC SYMBOL
Q0 Q0 Q1 Q1
56
98
VCC = Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0
D1
212
SF00046
IEC/IEEE SYMBOL
4
3
2
1
10
11
12
13
5
6
9
8
&
S
C1
C2
R
1D
2D
R
SF00047
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