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參數(shù)資料
| 型號： | 933593460652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | 4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 49K |
| 代理商： | 933593460652 |
92
XMEGA E5 [DATASHEET]
8153G–AVR–10/2013
Notes:
1.
Required only for fSCL > 100kHz.
2.
Cb = Capacitance of one bus line in pF.
3.
fPER = Peripheral clock frequency.
tLOW
Low period of SCL Clock
fSCL ≤ 100kHz
4.7
s
fSCL ≤ 400kHz
1.3
fSCL ≤ 1MHz
0.5
tHIGH
High period of SCL Clock
fSCL ≤ 100kHz
4
s
fSCL ≤ 400kHz
0.6
fSCL ≤ 1MHz
0.26
tSU;STA
Set-up time for a repeated START
condition
fSCL ≤ 100kHz
4.7
s
fSCL ≤ 400kHz
0.6
fSCL ≤ 1MHz
0.26
tHD;DAT
Data hold time
fSCL ≤ 100kHz
0
3.45
s
fSCL ≤ 400kHz
0
0.9
fSCL ≤ 1MHz
0
0.45
tSU;DAT
Data setup time
fSCL ≤ 100kHz
250
ns
fSCL ≤ 400kHz
100
fSCL ≤ 1MHz
50
tSU;STO
Setup time for STOP condition
fSCL ≤ 100kHz
4
s
fSCL ≤ 400kHz
0.6
fSCL ≤ 1MHz
0.26
tBUF
Bus free time between a STOP and
START condition
fSCL ≤ 100kHz
4.7
s
fSCL ≤ 400kHz
1.3
fSCL ≤ 1MHz
0.5
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
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