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參數(shù)資料
| 型號： | 933507930652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDIP24 |
| 封裝： | PLASTIC, SOT-101-1, DIP-24 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 55K |
| 代理商： | 933507930652 |
January 1995
5
Philips Semiconductors
Product specication
Programmable divide-by-n counter
HEF4059B
LSI
FUNCTION TABLE
Note
1. It is recommended that the device is in the master preset mode (Kb =Kc = logic 0) in order to correctly initialize the
device prior to start up.
2. H = HIGH voltage level
L = LOW voltage level
X = don’t care
DC CHARACTERISTICS
VSS =0 V
LATCH
ENABLE
INPUT
MODE
SELECT
INPUTS
FIRST COUNTING
SECTION
DECADE 1
LAST COUNTING
SECTION
DECADE 5
COUNTER
RANGE
OPERATION
LE
Ka
Kb
Kc
MODE
MAX.
PRESET
STATE
JAM
INPUTS
USED
DIVIDE
BY
MAX.
PRESET
STATE
JAM
INPUTS
USED
BCD
MAX.
BINARY
MAX.
HH
H
2
1
J1
87
J2J3J4
15 999 17 331
timer mode
HL
H
4
3
J1J2
43
J3J4
15 999 18 663
HH
L
H
5
4
J1J2J3
21
J4
9 999 13 329
HL
L
H
8
7
J1J2J3
21
J4
15 999 21 327
HH
H
L
10
9
J1J2J3J4 10
9 999 16 659
LH
H
2
1
J1
87
J2J3J4
15 999 17 331
divide-by-n mode
LL
H
4
3
J1J2
43
J3J4
15 999 18 663
LH
L
H
5
4
J1J2J3
21
J4
9 999 13 329
LL
L
H
8
7
J1J2J3
21
J4
15 999 21 327
LH
H
L
10
9
J1J2J3J4 10
9 999 16 659
HL
H
L
10
9
J1J2J3J4 10
9 999 16 659
L
H
L
preset inhibited
xed
10 000
divide-by-10 000
mode
XX
L
master preset
master preset
mode
VDD
V
SYMBOL
Tamb (°C)
UNIT
40
MIN.
+ 25
MIN.
+ 85
MIN.
Output (sink)
4,75
2,7
2,3
1,8
mA
VO =
0,4 V; VI = 0 or 4,75 V
current LOW
10
IOL
9,5
8
6,3
mA
VO =
0,5 V; VI = 0 or 10 V
15
24
20
16
mA
VO =
1,5 V; VI = 0 or 15 V
Output (source)
5
0,8
0,7
0,5
mA
VO =
4,6 V; VI = 0 or 5 V
current HIGH
10
I
OH
2,4
2
1,6
mA
VO =
9,5 V; VI = 0 or 10 V
15
8,4
7
5,6
mA
VO = 13,5 V; VI = 0 or 15 V
Output (source)
current HIGH
5
I
OH
2,4
2
1,6
mA
VO = 2,5 V; VI = 0 or
5 V
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