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參數(shù)資料
| 型號： | 933406850652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT DOWN BINARY COUNTER, PDSO16 |
| 封裝： | PLASTIC, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 106K |
| 代理商： | 933406850652 |
January 1995
7
Philips Semiconductors
Product specication
Programmable 4-bit binary down counter
HEF4526B
MSI
AC CHARACTERISTICS
VSS =0V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
Note
1. In the divide-by-n mode (PL connected to TC), one has to observe the maximum HIGH to LOW propagation delay
for CP to TC, before applying the next clock pulse.
VDD
V
SYMBOL
MIN.
TYP.
MAX.
Minimum clock
5
80
40
ns
see also waveforms
Figs 5 and 6
pulse width CP0
10
tWCPL
40
20
ns
LOW
15
30
15
ns
Minimum clock
5
80
40
ns
pulse width CP1
10
tWCPH
40
20
ns
HIGH
15
30
15
ns
Minimum PL
5
100
50
ns
pulse width; HIGH
10
tWPLH
40
20
ns
15
32
16
ns
Minimum MR
5
130
65
ns
pulse width; HIGH
10
tWMRH
50
25
ns
15
40
20
ns
Hold time
5
30
5
ns
Pn → PL
10
thold
20
5
ns
15
5
ns
Set-up time
5
30
0
ns
Pn → PL
10
tsu
20
0
ns
15
0
ns
Maximum clock
5
6
12
MHz
see note 1
pulse frequency
10
fmax
12
25
MHz
PL = LOW
15
16
32
MHz
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