參數(shù)資料
型號： 933372930653
廠商： NXP SEMICONDUCTORS
元件分類： 門電路
英文描述： 4000/14000/40000 SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO16
封裝： PLASTIC, SOT-109-1, SO-16
文件頁數(shù)： 4/4頁
文件大小： 30K
代理商： 933372930653
January 1995
4
Philips Semiconductors
Product specication
HEX non-inverting buffers
HEF4050B
buffers
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
5
35
70
ns
26 ns
+ (0,18 ns/pF) CL
In
On
10
tPHL
20
35
ns
16 ns
+ (0,08 ns/pF) CL
HIGH to LOW
15
30
ns
12 ns
+ (0,05 ns/pF) CL
5
55
110
ns
28 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
25
55
ns
14 ns
+ (0,23 ns/pF) CL
15
20
40
ns
12 ns
+ (0,16 ns/pF) CL
Output transition
5
25
50
ns
7 ns
+ (0,35 ns/pF) CL
times
10
tTHL
10
20
ns
3 ns
+ (0,14 ns/pF) CL
HIGH to LOW
15
7
14
ns
2 ns
+ (0,09 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
3 800 fi +∑ (foCL) × VDD2
where
dissipation per
10
11 600 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
65 900 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
相關(guān)PDF資料
PDF描述
933372990653 4000/14000/40000 SERIES, 8-INPUT NAND GATE, PDSO14
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