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參數(shù)資料
| 型號： | 933282630652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 7-BIT UP BINARY COUNTER, PDIP14 |
| 封裝： | PLASTIC, SOT-27-1, DIP-14 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 41K |
| 代理商： | 933282630652 |
January 1995
2
Philips Semiconductors
Product specication
7-stage binary counter
HEF4024B
MSI
DESCRIPTION
The HEF4024B is a 7-stage binary ripple counter with a
clock input (CP), and overriding asynchronous master
reset input (MR) and seven fully buffered parallel outputs
(O0 to O6). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of CP. Each
counter stage is a static toggle flip-flop.
Fig.1 Functional diagram.
HEF4024BP(N):
14-lead DIL; plastic
(SOT27-1)
HEF4024BD(F):
14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4024BT(D):
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
APPLICATION INFORMATION
Some examples of applications for the HEF4024B are:
Frequency dividers
Time delay circuits
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
CP
clock input (HIGH to LOW triggered)
MR
master reset input
O0 to O6
buffered parallel outputs
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