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參數(shù)資料
| 型號： | 932S421BGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 333.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 220K |
| 代理商： | 932S421BGLF |
IDTTM
PCIe Gen2 and QPI Clock for Intel-Based Servers
1340G—01/26/10
ICS932S421B
PCIe Gen2 and QPI Clock for Intel-Based Servers
19
PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.
When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is
de-asserted.
PD, Power Down
D
PU
P
C#
U
P
CC
R
S#
C
R
SI
C
P
/
F
I
C
PB
S
UF
E
Re
t
o
N
0l
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nz
H
M
3
3z
H
M
8
4z
H
M
8
1
3
.
4
11
1r
o
2
*
f
e
r
I
t
a
o
l
F
t
a
o
l
F2
*
f
e
r
I
t
a
o
l
F
r
o
t
a
o
l
Fw
o
Lw
o
Lw
o
L1
Notes:
1. Refer to SMBus Byte 4 for additional information.
PD should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x
Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
See SMBus Bytes 4 and 5 for additional information.
PD Assertion
PD
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
REF Drive Strength Functionality
Byte6,
bit 4
Byte
10, bit 1
Byte 10,
bit 0
REF1
REF0
0
XX1x
1x
10
0
1x
10
1
1x
2x
11
0
2x
1x
11
1
2x
CPU, SRC and PCI Divider Ratios
Div(3:0)
Divider
00000
2
10001
3
20010
5
30011
15
40100
4
50101
6
60110
10
70111
30
81000
8
91001
12
10
1010
20
11
1011
60
12
1100
16
13
1101
24
14
1110
40
15
1111
120
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 932S421BGLFT | 功能描述:時鐘合成器/抖動清除器 CK410B+ SERVER MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S421CFLF | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S421CFLFT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S421CGLF | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S421CGLFT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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