參數(shù)資料
型號(hào): 932S401EGLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁(yè)數(shù): 11/23頁(yè)
文件大小: 195K
代理商: 932S401EGLF
19
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.
When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is
de-asserted.
PD, Power Down
D
PU
P
C#
U
P
CC
R
S#
C
R
SI
C
P
/
F
I
C
PB
S
UF
E
Re
t
o
N
1l
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nz
H
M
3
3z
H
M
8
4z
H
M
8
1
3
.
4
11
0r
o
2
*
f
e
r
I
t
a
o
l
F
t
a
o
l
F2
*
f
e
r
I
t
a
o
l
F
r
o
t
a
o
l
Fw
o
Lw
o
Lw
o
L1
Notes:
1. Refer to SMBus Byte 4 for additional information.
PD# should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x
Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
See SMBus Byte 4 for additional information.
PD Assertion
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
相關(guān)PDF資料
PDF描述
932S401EFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
932S421BGLF 333.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
932S421BGLFT 333.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
932S421BFLFT 333.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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