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參數(shù)資料
| 型號： | 932S208YGLNT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, LEAD FREE, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 151K |
| 代理商： | 932S208YGLNT |
IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor
0743G—01/26/10
ICS932S208
Programmable Timing Control HubTM for Next Gen P4TM Processor
3
Pin Description (continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
29
3V66_4/VCH
OUT
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
30
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
31
48MHz_USB
OUT
48MHz clock output.
32
48MHz_DOT
OUT
48MHz clock output.
33
GND
PWR
Ground pin.
34
VDD48
PWR
Power pin for the 48MHz output.3.3V
35
Vtt_PWRGD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
36
VDD
PWR
Power supply for SRC clocks, nominal 3.3V
37
SRCCLKC
OUT
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
38
SRCCLKT
OUT
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
39
GND
PWR
Ground pin.
40
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
42
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
43
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
45
GND
PWR
Ground pin.
46
CPUCLKC2
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
47
CPUCLKT2
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
48
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
49
CPUCLKC3
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
50
CPUCLKT3
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
51
FS_A
IN
Frequency select pin, see Frequency table for functionality
52
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
53
GND
PWR
Ground pin.
54
GNDA
PWR
Ground pin for core.
55
VDDA
PWR
3.3V power for the PLL core.
56
FS_B
IN
Frequency select pin, see Frequency table for functionality
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 932S401EFLF | 功能描述:時(shí)鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S401EFLFT | 功能描述:時(shí)鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S401EGLF | 功能描述:時(shí)鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S401EGLFT | 功能描述:時(shí)鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S421BFLF | 功能描述:時(shí)鐘合成器/抖動清除器 CK410B+ SERVER MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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