參數(shù)資料
型號: 932S208DGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP
文件頁數(shù): 18/22頁
文件大?。?/td> 231K
代理商: 932S208DGLFT
5
Integrated
Circuit
Systems, Inc.
ICS932S208
0743D—07/07/04
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
VDD + 0.5V
V
VDD_In
3.3V Logic Input Supply Voltage
GND - 0.5
VDD + 0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protection
human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
Input MID Voltage
VMID
3.3 V +/-5%
1
1.8
V
Input Low Voltage
VIL
3.3 V +/-5%
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
uA
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5
uA
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
Operating Supply Current
IDD3.3OP
Full Active, CL = Full load;
350
mA
all diff pairs driven
35
mA
all differential pairs tri-stated
12
mA
Input Frequency
3
Fi
VDD = 3.3 V
14.31818
MHz
3
Pin Inductance
1
Lpin
7nH
1
CIN
Logic Inputs
5
pF
1
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
Clk Stabilization
1,2
TSTAB
From VDD Power-Up or de-
assertion of PD# to 1st clock
1.8
ms
1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_SRC
SRC output enable after
PCI_Stop# de-assertion
15
ns
1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
us
1
Tfall_Pd#
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
2
Tdrive_CPU_Stop#
CPU output enable after
CPU_Stop# de-assertion
10
us
1
Tfall_CPU_Stop#
PD# fall time of
5
ns
1
Trise_CPU_Stop#
PD# rise time of
5
ns
2
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
IDD3.3PD
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
Input Capacitance
1
Input Low Current
Powerdown Current
相關(guān)PDF資料
PDF描述
932S208DGT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
932S208DFLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
932S208DFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
932S208DFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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